bet188金宝搏

图书馆IEEE;
使用IEEE.STD_LOGIC_1164.ALL;
使用IEEE.STD_LOGIC_ARITH.ALL;
使用IEEE.STD_LOGIC_SIGNED.ALL;

实体radix4_butterfly_r是
端口(CLK:在std_logic;——处理时钟
重置:在std_logic;——异步复位信号
Ri0: in std_logic_vector(15 downto 0);——input1实部
Ri1: in std_logic_vector(15 downto 0);——input2实部
Ri2: in std_logic_vector(15 downto 0);——input3实部
Ri3: in std_logic_vector(15 downto 0);——input4实数部分
Ii0: in std_logic_vector(15 downto 0);——input1虚部
Ii1: in std_logic_vector(15 downto 0);——input2虚部
Ii2: in std_logic_vector(15 downto 0);——input3虚部
Ii3: in std_logic_vector(15 downto 0);——input4虚部
Co1: in std_logic_vector(15 downto 0);——Cos角1
Co2:在std_logic_vector(15下降到0);Cos角2
Co3: in std_logic_vector(15 downto 0);——Cos角3
Si1: in std_logic_vector(15 downto 0);——角度的正弦值
Si2: in std_logic_vector(15 downto 0);——角度的正弦值
Si3: in std_logic_vector(15 downto 0);——角度的正弦值
Ro0: out std_logic_vector(15 downto 0);——output1的实部
Ro1: out std_logic_vector(15 downto 0);——输出2的实部
Ro2: out std_logic_vector(15 downto 0);——output3的实部分
Ro3: out std_logic_vector(15 downto 0);——输出的实数部分
Io0: out std_logic_vector(15 downto 0);——输出t1的虚部
Io1: out std_logic_vector(15 downto 0);——输出的虚部2
Io2: out std_logic_vector(15 downto 0);——输出的虚部
Io3: out std_logic_vector(15 downto 0)——输出4的虚部
）;
radix4_butterfly_r结束;

radix4_butterfly_r的行为是
——真实信号——
信号r1: std_logic_vector(15 downto 0);
信号r2: std_logic_vector(15 downto 0);
信号r3: std_logic_vector(15 downto 0);
信号r4: std_logic_vector(15 downto 0);
信号r5: std_logic_vector(15 downto 0);
信号t1: std_logic_vector(15 downto 0);
信号t3: std_logic_vector(15 downto 0);
信号sig_ro2: std_logic_vector(31 downto 0);
信号sig_ro1: std_logic_vector(31 downto 0);
信号sig_ro3: std_logic_vector(31 downto 0);
——图像信号——

信号s1: std_logic_vector(15 downto 0);
s2: std_logic_vector(15 downto 0);
s3: std_logic_vector(15 downto 0);
信号s4: std_logic_vector(15 downto 0);
信号s5: std_logic_vector(15 downto 0);
信号t2: std_logic_vector(15 downto 0);
信号t4: std_logic_vector(15 downto 0);
信号sig_io2: std_logic_vector(31 downto 0);
信号sig_io1: std_logic_vector(31 downto 0);
信号sig_io3: std_logic_vector(31 downto 0);
信号co11, co21, co31: std_logic_vector(15 downto 0);
信号si11, si21, si31: std_logic_vector(15 downto 0);
信号co12, co22, co32: std_logic_vector(15 downto 0);
信号si12, si22, si32: std_logic_vector(15 downto 0);
信号mull_r3_co2: std_logic_vector(31 downto 0);
信号mull_s3_si2: std_logic_vector(31 downto 0);
信号mull_s3_co2: std_logic_vector(31 downto 0);
信号mull_r3_si2: std_logic_vector(31 downto 0);
信号mull_r4_co1: std_logic_vector(31 downto 0);
信号mull_s4_si1: std_logic_vector(31 downto 0);
信号mull_s4_co1: std_logic_vector(31 downto 0);
信号mull_r4_si1: std_logic_vector(31 downto 0);
信号mull_r5_co3: std_logic_vector(31 downto 0);
信号mull_s5_si3: std_logic_vector(31 downto 0);
信号mull_s5_co3: std_logic_vector(31 downto 0);
信号mull_r5_si3: std_logic_vector(31 downto 0);
信号ro01: std_logic_vector(15 downto 0);
信号io01: std_logic_vector(15 downto 0);
开始
过程(时钟、复位)
开始
如果reset = '1'，则
R1 <= (others => '0');
R2 <= (others => '0');
T1 <= (others => '0');
S1 <= (others => '0');
S2 <= (others => '0');
T2 <= (others => '0');
T4 <= (others => '0');
T3 <= (others => '0');
Elsif CLK = '1'和CLK '事件则
R1 <= ri0 +ri2;
R2 <= ri0 -ri2;
T1 <= ri1 +ri3;
S1 <= ii0 +ii2;
S2 <= ii0 -ii2;
T2 <= ii1 +ii3;
T4 <= ii1 -ii3;
T3 <= ri1 - ri3;
如果;
结束过程;

过程(时钟、复位)
开始
如果reset = '1'，则
R3 <= (others => '0');
S3 <= (others => '0');
R4 <= (others => '0');
R5 <= (others => '0');
S4 <= (others => '0');
S5 <= (others => '0');
Co11 <= (others => '0');
Co21 <= (others => '0');
Co31 <= (others => '0');
Si11 <= (others => '0');
Si21 <= (others => '0');
Si31 <= (others => '0');
Co12 <= (others => '0');
Co22 <= (others => '0');
Co32 <= (others => '0');
Si12 <= (others => '0');
Si22 <= (others => '0');
Si32 <= (others => '0');
Ro0 <= (others => '0');
Io0 <= (others => '0');
Mull_r3_co2 <= (others => '0');
Mull_s3_si2 <= (others => '0');
Mull_s3_co2 <= (others => '0');
Mull_r3_si2 <= (others => '0');
Mull_r4_co1 <= (others => '0');
Mull_s4_si1 <= (others => '0');
Mull_s4_co1 <= (others => '0');
Mull_r4_si1 <= (others => '0');
Mull_r5_co3 <= (others => '0');
Mull_s5_si3 <= (others => '0');
Mull_s5_co3 <= (others => '0');
Mull_r5_si3 <= (others => '0');
Ro01 <= (others => '0');
Io01 <= (others => '0');
Elsif rising_edge(clk)然后
R3 <= r1 -t1;
S3 <= s1 -t2;
R4 <= r2 - t4;
R5 <= r2 + t4;
S4 <= s2 + t3;
S5 <= s2 - t3;
Co11 <= co1;
Co21 <= co2;
Co31 <= co3;
Si11 <= si1;
Si21 <= si2;
Si31 <= si3;
Co12 <= co11;
Co22 <= co21;
Co32 <= co31;
Si12 <= si11;
Si22 <= si21;
Si32 <= si31;
Ro01 <= r1 + t1;
Io01 <= s1 + t2;
Ro0 <= ro01;
Io0 <= io01;
Mull_r3_co2 <= r3*co22;
Mull_s3_si2 <= s3*si22;
Mull_s3_co2 <= s3*co22;
Mull_r3_si2 <= r3*si22;
Mull_r4_co1 <= r4*co12;
Mull_s4_si1 <= s4*si12;
Mull_s4_co1 <= s4*co12;
Mull_r4_si1 <= r4*si12;
Mull_r5_co3 <= r5*co32;
Mull_s5_si3 <= s5*si32;
Mull_s5_co3 <= s5*co32;
Mull_r5_si3 <= r5*si32;

如果;
结束过程;

——ro2的实际操作
Sig_ro2 <= (mull_r3_co2)+(mull_s3_si2);
Ro2 <= sig_ro2(23 ~ 8);

——io2的imag操作
Sig_io2 <= (mull_s3_co2)-(mull_r3_si2);
Io2 <= sig_io2(23 downto 8);

Sig_ro1 <= (mull_r4_co1)+(mull_s4_si1);
Ro1 <= sig_ro1(23 ~ 8);

——io1的imag操作
Sig_io1 <= (mull_s4_co1)-(mull_r4_si1);
Io1 <= sig_io1(23下降到8);

——ro3的实际操作
Sig_ro3 <= (mull_r5_co3)+(mull_s5_si3);
Ro3 <= sig_ro3(23下降到8);

——io3的imag操作
Sig_io3 <= (mull_s5_co3)-(mull_r5_si3);
Io3 <= sig_io3(23 downto 8);

端行为;