4位二进制到灰色计数器转换器HDL Verilog代码
本页verilog源代码里涵盖了4位二进制到灰色计数器转换器使用verilog。
象征
下面是4位二进制到灰色计数器转换器的符号和真值表。
真值表
Rst | Clk | 在 | B3 | B2 | B1 | B0 | G3 | G2 | G1 | G0 |
---|---|---|---|---|---|---|---|---|---|---|
1 | X | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 |
0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 |
0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 |
0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 |
0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 1 |
0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 |
0 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 0 |
0 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 0 |
0 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 |
0 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 1 |
0 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 |
0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 0 |
0 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 1 | 1 |
0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 1 |
0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |
Verilog代码
模块b2g (b、g);
输入[3:0]b;
输出[3:0]g;
xor (g [0], [0] b, b [1]),
(g [1], [1], [2] b),
(g [2], [2], [3] b);
分配b g [3] = [3];
终端模块
仿真结果
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